1. Field of the Invention
The invention relates to field effect transistors and more particularly to fin field effect transistors and to such structures that have different height fins.
2. Description of Related Art
Since 1960 when integrated circuits (“ICs”) were first created and fabricated, the number and density of the devices being formed on IC substrates has tremendously. Indeed, the very large scale integration (“VLSI”) devices, having more than 100,000 devices on a chip, are generally considered old technology. The fabrication of ICs having hundreds of millions of devices on a chip is standard in the market today. The development of ICs with billions of devices on each chip is under current development. Therefore, the current description of IC fabrication is ultra large scale integration (“ULSI”).
As part of the increase in the number of devices formed on an IC substrate and the concurrent increase in density of the devices, the dimensions of the devices have dropped significantly. In particular, the dimensions of gate thicknesses and channel separation of source and drain elements have continually reduced such that today micrometer and nanometer separations of the source, drain, and gate are required. Although devices have been steadily reduced in size, the performance of the devices must be maintained or improved. In addition to performance characteristics, performance reliability, and durability of the device, the manufacturing reliability and cost are always critical issues.
Several problems arise with the miniaturization of devices, including short channel effects, punch-through, and current leakage. These problems affect both the performance of the device and the manufacturing process. The impact of short channel effects on device performance is seen in the reduction in the device threshold voltage and the increase of sub-threshold current.
More particularly, as the channel length becomes smaller, the source and drain depletion regions get closer to each other. The depletion regions may essentially occupy the entire channel area between the source and drain. As a result of this effective occupation of the channel area by the source and drain depletion regions, the channel is in part depleted and the gate charge necessary to alter the source and drain current flow is reduced.
One method for reducing or eliminating short channel effects is to reduce the thickness of the gate oxides adjacent to the source and drain. Not only will thin gate oxides reduce short channel effects, but they also allow for higher drive currents. One result is faster devices. As can be expected, however, there are significant problems associated with fabricating thin oxides, including manufacturing reproducibility and the uniformity and control of the oxide growth rate during the fabrication process.
To resolve the short channel effects and other problems associated with ULSI, improvements to devices have been made and are continuing. One such attempt, described in U.S. Pat. No. 6,252,284 to Muller et al. (hereinafter “Muller”, which is incorporated herein by reference) discloses a field effect transistor (FET) that includes a channel region that has a fin shape and that is referred to as a FinFET device. This is shown in FIG. 1. In a FinFET type structure, the channel 24 and source and drain regions 4 are formed as a vertical silicon fin structure extending from a substrate 5. The vertical gate structure 21 intersects the channel region 24 of the fin structure. While not shown in FIG. 1, various insulator layers separate the channel region 24 from the gate 21. FIG. 1 also illustrates an oxide layer 20, and insulating sidewall spacers 12, 23 formed on the fin structure 4, 24 and the gate structure 21. The ends of the fin structure 4 receive source and drain doping implants that make these regions of the fin structure conductive. The channel region 24 of the fin structure is doped so that the silicon comprises a semiconductor, which only becomes conductive when sufficient voltage/current is present in the gate 21.
However, conventional FinFET devices are formed so that all FinFET transistors have the same fin height on a given chip. The invention described below provides a method to produce different fin heights on a single chip and a method of selecting the proper ratios between the different heights of the different fins.